MU42 is a 4-input to 1-output digital multiplexer with 2x drive strength.

Truth Table

I0

I1

S1

Q

S0

I2

I3

Capacitance

S1

S0

Q

Ci (pF)

L

L

I0

I0

0.026

L

H

I1

I1

0.021

H

L

I2

I2

0.024

H

H

I3

I3

0.015

S0

0.064

S1

0.029

Area

Power

1.49 mils

2

4.20 µW / MHz

Delay [ns] = tpd.. = f(SL, L)

with SL = Input Slope [ns] ; L = Output Load [pF]

Output Slope [ns] = op_sl.. = f(L)

with L = Output Load [pF]

AC Characteristics :

Tj = 25°C

VDD = 3.3V

Typical Process

AC Characteristics

Characteristics

Symbol

SL = 0.1

SL = 2.0

L = 0.2

L = 1.4

L = 2.0

L = 0.2

L = 1.4

L = 2.0

Delay I0 to Q

tpdi0r

1.06

3.73

5.21

1.11

3.92

5.32

tpdi0f

0.99

2.91

3.95

1.16

3.10

4.14

Delay I1 to Q

tpdi1r

1.04

3.72

5.16

1.10

3.88

5.13

tpdi1f

1.01

2.92

3.93

1.17

3.13

4.04

Delay I2 to Q

tpdi2r

1.01

3.79

5.03

1.05

3.85

5.18

tpdi2f

1.40

3.32

4.31

1.60

3.52

4.50

Delay I3 to Q

tpdi3r

1.03

3.74

5.25

1.08

3.87

5.11

tpdi3f

1.39

3.31

4.24

1.58

3.50

4.49

Delay S0 to Q

tpds0r

1.36

4.07

5.53

1.68

4.35

5.88

tpds0f

1.61

3.52

4.49

1.80

3.72

4.70

Delay S1 to Q

tpds1r

0.82

3.62

4.92

1.00

3.77

5.02

tpds1f

0.76

2.73

3.71

1.08

2.97

4.03

Output Slope I0 to Q

op_sli0r

1.83

10.02

14.41

1.78

10.13

14.35

op_sli0f

1.32

6.78

9.66

1.32

6.82

9.61

Output Slope I1 to Q

op_sli1r

1.83

10.02

14.41

1.78

10.17

14.13

op_sli1f

1.33

6.78

9.46

1.33

6.82

9.58

Output Slope I2 to Q

op_sli2r

1.85

10.18

14.27

1.83

10.13

14.40

op_sli2f

1.45

6.75

9.51

1.42

6.76

9.43

Sept. 1996

- 216 -

Rev. N/C

Austria Mikro S ysteme International

R

0.6 µm CMOS

CUB

MU42

MU42