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ARA2004 Datasheet(PDF) 12 Page - ANADIGICS, Inc |
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ARA2004 Datasheet(HTML) 12 Page - ANADIGICS, Inc |
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12 / 20 page ![]() 12 Data Sheet - Rev 2.1 07/2005 ARA2004 DATA CLOCK ENABLE ENABLE OR D 7: MSB D 6 D 4 D 3 D 1 D 0: LSB Table 6: Programming Word T I B A T A D D7 D6 D5 D4 D3 D2 D1 D0 e u l a V 7 P6 P5 P4 P3 P2 P1 P0 P LOGIC PROGRAMMING Table 7: Data Description Figure 17: Serial Data Input Timing E U L A V N O I T C N U F ) s s a p y b = 0 , n o = 1 ( 7 PA / N 6 PA / N 5 Pti B r o t a u n e tt A B d 2 3 4 Pti B r o t a u n e tt A B d 6 1 3 Pti B r o t a u n e tt A B d 8 2 Pti B r o t a u n e tt A B d 4 1 Pti B r o t a u n e tt A B d 2 0 Pti B r o t a u n e tt A B d 1 Programming Instructions The programming word is set through an 8 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register. |
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