important to provide a large heat spreading pad on the

opposite side of the board. The vias will provide a good

thermal connection between the pad under the IC, and the

heat spreading pad on the bottom of the board. Thermal

modelling can be done using the

θ junction to pad informa-

tion provided, to calculate the required area of copper based

on the ambient temperature of the system, and the calcu-

lated amount of thermal dissipation in the LM98555.

POWER DISSIPATION

The amount of power dissipated in the device can be deter-

mined by considering the following factors:

•

Power dissipated delivering energy to the load capaci-

tance

•

Power dissipated delivering energy to parasitic capaci-

tance

•

Power dissipated due to leakage in the IC

The amount of power dissipated due to leakage is very small

in this CMOS device. Most of the power will be due to the

load capacitance being switched, with a small additional

amount caused by the parasitic capacitance of the output

circuitry, output pins, and PCB traces. A typical parasitic

capacitance would be on the order of 5 pF. Since the load

capacitance will be on the order of 100 pF or more, this

usually dominates the power dissipation calculation. The

following equation can be used to calculate the power dissi-

pation due to capacitive switching of the loads:

P = Sum[Output Frequency x Load Capacitance x Output

Voltage Squared] (summed for all outputs)

INPUT SIGNALS

Care should be taken to match the trace lengths between

timing signals that require low skew. Usually, the P1A and

P2A signals will be the most critical. In some applications,

the timing of P2B with respect to P1A and P2A can also be

important, and that input trace should also be carefully de-

signed.

Trace shape and width should also be carefully controlled.

The trace geometry will determine the characteristic imped-

ance of each trace. The impedance should be set to give

reasonable immunity to noise coupling into the trace. With a

known trace impedance, the signals can be terminated using

a series resistor at the source that is equal to the character-

istic impedance. This will provide a signal with minimum

overshoot and ringing, and will contribute to better perfor-

mance of the final signal reaching the CCD.

OUTPUT CONNECTIONS AND LOADING EXAMPLES

The LM98555 can be used with a wide variety of different

CCD sensors. The P1Aoutx and P2Aoutx outputs can be

selectively enabled to provide 2, 4, 6, or 8 drivers. This

allows the available drive strength to be optimized for the

sensor and application. Connecting multiple outputs together

in parallel as shown in the typical application circuit provides

lower drive impedance as needed to suit the load being

driven. When driving smaller loads, lower switching noise

will be generated if the minimum necessary outputs are

enabled and used.

The output signal traces should also be designed for a

known impedance. Source terminating resistors should be

used in series with each output to provide good matching to

the trace characteristic impedance. The resistors should be

located as close as possible to each output pin. If multiple

outputs will be combined to drive a single load pin, the output

signals should be combined after the termination resistors.

This will provide the best summing of adjacent outputs. The

combined signal should then pass through an EMI type

ferrite bead. This component can be selected to change the

bandwidth or shape of the clocking signal to achieve the best

CCD transfer efficiency.

Several other techniques will also help maintain signal qual-

ity, and minimize timing differences between critical signals.

Vias should not be used for critical timing signals. These can

add impedance discontinuities that will affect the waveform

quality. Traces should have gradual bends and avoid sharp

changes in direction that can also introduce impedance dis-

continuities.

SELECTIVE DRIVER ENABLING

With the Enable pins, the user has the capability to enable

only the drivers that are required for the application, thus

eliminating unnecessary outputs switching. The following

table shows the details.

EN1

EN0

Driver-set State

0

0

P1Aout(1:0) and P2Aout(1:0) are enabled;

all others disabled.

0

1

P1Aout(3:0) and P2Aout(3:0) are enabled;

all others disabled.

1

0

P1Aout(5:0) and P2Aout(5:0) are enabled;

all others disabled.

1

1

All P1Aout and P2Aout drivers are enabled.

Note: The disabled drivers’ outputs are in TRI-STATE.

POWER AND GROUND - PLANES VERSUS BUSES

The best performance will be achieved by using planes

rather than traces for power and ground. Planes provide

lower electrical and thermal impedance. Ground bounce and

ringing are reduced, electromagnetic emissions are mini-

mized and the best thermal performance will be realized.

A single common ground plane should be used for all power

and signal domains.

Another circuit board layer can be used to provide power to

the various circuitry. Different power buses can be provided

by isolated planes within this layer of the circuit board.

EMI MANAGEMENT

Good EMI control will be achieved by addressing the follow-

ing items:

•

Provide proper source termination of output signals

•

Limit length of output traces

•

Ensure adequate power supply decoupling

•

Provide power and ground planes as much as possible

•

Provide common ground plane for all signals, especially

between LM98555 outputs and load CCD

•

Enable and use the minimum number of outputs needed

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