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DS20005018B-page 21

SST39VF1601C/SST39VF1602C

FIGURE 8-7:

WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM

FIGURE 8-8:

WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM

1380 F32.0

ADDRESSES

DQ15-0

WE#

555

2AA

2AA

555

555

XX55

XX30

XX55

XXAA

XX80

XXAA

BAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

TBE

TBY

TBR

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable

as long as minimum timings are met. (See Table 8-2).

BAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

1380 F28.0

ADDRESSES

DQ15-0

WE#

555

2AA

2AA

555

555

XX55

XX50

XX55

XXAA

XX80

XXAA

SAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

TSE

TBY

TBR

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable

as long as minimum timings are met. (See Table 8-2).

SAX = Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.