ADC12DL080EVAL datasheet(20/24 Pages) NSC

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Applications Information (Continued)

with a series RC to ground such that the resistor value is

equal to the characteristic impedance of the clock line and

the capacitor value is

where t

PD is the signal propagation rate down the clock line,

"L" is the line length and Z

O is the characteristic impedance

of the clock line. This termination should be as close as

possible to the ADC clock pin but beyond it as seen from the

clock source. Typical t

PD is about 150 ps/inch (60 ps/cm) on

FR-4 board material. The units of "L" and t

PD should be the

same (inches or centimeters).

The duty cycle of the clock signal can affect the performance

of the A/D Converter. Because achieving a precise duty

cycle is difficult, the ADC12DL080 has a Duty Cycle Stabi-

lizer which can be enabled using the REFSEL/DCS pin. It is

designed to maintain performance over a clock duty cycle

range of 30% to 70% at 80 MSPS.

2.2 REFSEL/DCS

This pin is used in conjunction with V

REF (pin 7) to select the

reference source and turn the Duty Cycle Stabilizer (DCS)

on or off.

When REFSEL/DCS is LOW and V

REF is HIGH, the internal

1.0V reference is selected and DCS is On.

When REFSEL/DCS is HIGH, an external reference voltage

in the range of 0.8V to 1.2V should be applied to the VREF

input. DCS is On.

With this pin connected to V

RMAor VRMB, DCS is Off.

When enabled, duty cycle stabilization can compensate for

clock inputs with duty cycles ranging from 30% to 70% and

generate a stable internal clock, improving the performance

of the part.

TABLE 3. V

REF, REFSEL/DCS Pin Functions

REFSEL/DCS (pin 11) V

REF (pin 7)

Reference

DCS

Logic LOW

Logic HIGH

Internal 1.0 V ON

Logic High

0.8 to 1.2V

External

RMAor VRMB

Logic High

Internal 1.0V

OFF

RMAor VRMB

0.8 to 1.2V

External

OFF

2.3 OF/DOEN, OEA/OF, and OEB/DRDY

OF/DOEN (pin 21) selects the output format (OF) or enables

the DRDY output (DOEN). The state of this pin also controls

the function of pins 22 (OEA/OF) and 41 (OEB/DRDY).

When OF/DOEN is tied to V

RMAor VRMB, DRDY is enabled.

Pin 41 is used as the DRDY output strobe, and pin 22 is used

to select the output format. Output Enable for channels A and

B are not available in this mode.

When OF/DOEN is LOW, the output data format is offset

binary. With OF/DOEN tied HIGH, the output format is 2’s

complement.

The following table describes the function of these pins.

TABLE 4. OF/DOEN, OEA/OF, OEB/DRDY Pin Functions

Pin 21 State

Pin 21 Function

Pin 22 Function

Pin 41 Function

RMAor VRMB

DRDY output is enabled

Output Format

LOW = Offset Binary

HIGH = 2’s Complement

DRDY Output

Logic LOW

Output Format = Offset Binary

Output Enable for Channel A

LOW = outputs are enabled

HIGH = outputs are in high

impedance state

Output Enable for Channel B

LOW = outputs are enabled

HIGH = outputs are in high

impedance state

Logic HIGH

Output Format = 2’s Complement

2.4 PD

The PD pin, when high, holds the ADC12DL080 in a power-

down mode to conserve power when the converter is not

being used. The output data pins are undefined and the data

in the pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the

value of the components on pins 4, 5, 6, 12, 13 and 14.

These capacitors loose their charge in the Power Down

mode and must be recharged by on-chip circuitry before

conversions can be accurate. Smaller capacitor values allow

slightly faster recovery from the power down mode, but can

result in a reduction in SNR, SINAD and ENOB perfor-

mance.

3.0 OUTPUTS

The ADC12DL080 has 12 TTL/CMOS compatible Data Out-

put pins for each output. Valid data is present at these

outputs while the OE and PD pins are low. Be very careful

when driving a high capacitance bus. The more capacitance

the output drivers must charge for each conversion, the

more instantaneous digital current flows through V

DR and

DR GND. These large charging current spikes can cause

on-chip ground noise and couple into the analog circuitry,

degrading dynamic performance. Adequate bypassing, lim-

iting output capacitance and careful attention to the ground

plane will reduce this problem. Additionally, bus capacitance

beyond the specified 10 pF/pin will cause t

OD to increase,

making it difficult to properly latch the ADC output data. The

result could be an apparent reduction in dynamic perfor-

mance.

To minimize noise due to output switching, minimize the load

currents at the digital outputs. This can be done by connect-

ing buffers (74LVTH162374, for example) between the ADC

outputs and any other circuitry. Only one driven input should

be connected to each output pin. Additionally, inserting se-

ries resistors of about 100

Ω at the digital outputs, close to

the ADC pins, will isolate the outputs from trace and other

circuit capacitances and limit the output currents, which

could otherwise result in performance degradation. See Fig-

ure 4.

ADC12DL080EVAL Datasheet(PDF) 20 Page - National Semiconductor (TI)

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