SIP32434

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Vishay Siliconix

S22-0384-Rev. B, 02-May-2022

18

Document Number: 63147

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OTP, OVER-TEMPERATURE PROTECTION

Over-temperature protection turns off the power switch when the die temperature reaches the OTP threshold of 165 °C. The

hysteresis is 45 °C. When the die temperature drops below 120 °C, it is allowed to turn on again.

PGD, POWER GOOD REPORTING

PGD is an open drain output. A pull-up resistor must be connected pulling to 3 V or 5 V. It is asserted low when VOUT is below

95 % of VIN, or an over-current, over-voltage, or over-temperature fault condition occurs.

INPUT CAPACITOR

While bypass capacitors at the input pins are not required, a 2.2 μF or larger capacitors for CIN is recommended in almost all

applications. The bypass capacitors should be placed as physically close to the device’s input pins and ground to be effective

to minimize transients on the input. Ceramic capacitors are recommended over tantalum because of their ability to withstand

input current surges from low impedance sources such as batteries. For hot-plug applications, where input path inductance is

negligible, this input capacitor can be minimized or eliminated.

OUTPUT CAPACITOR

The SIP32434A and SIP32434B do not require an output capacitor for proper operation. A proper value COUT is recommended

to accommodate load transient per circuit design requirements. There are no ESR or capacitor type requirements.

Protection

LAYOUT GUIDELINES

The SIP32434A and SIP32434B are protection switches designed to maintain a constant output load current upon over-current

fault. Optimized layout with efficient heat sinking is critical. It is recommended to put as much copper as possible to the devices’

central exposed pad which is connected to ground. Connect all ground planes with all possible thermal VIAs.

The circuit setting components should be laid close to their connection pins. The components include current limit setting

resistor, soft start setting capacitor, and resistors connected to EN / UVLO and OVP pins.

Protection devices such as input TVS or output Schottky diodes must be located close the pins to be protected and routed with

short traces to reduce inductance.

Below is a layout example.

Fig. 41

CIN

COUT

RLIM

RPGD

ROVP2

D

GND

VOUT+

VIN+

ROVP1

CSS

1

4

2

3

56

10

9

8

7