LTC3113 datasheet(22/32 Pages) AD

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LT3154

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

–

COUT

VOUT

RLOAD

RESR

VCCS

VOLTAGE

ERROR

AMPLIFIER

gm = 110µA/V

gm VIN > VOUT: 10A/V

VIN > VOUT: (10A/V) • (VIN/VOUT)

3154 F05

0.99V

0.9V

CHF

VEA

–

Figure 5. Simplified Representation of

Average Current Mode Control Loop

The outer voltage loop requires external compensation

components, which allows the overall loop characteristics

to be customized depending on the programmed output

voltage, oscillator frequency, inductor value and/or output

capacitance. The average current mode control can be

conceptualized as a voltage‑controlled current source

(VCCS), driving the output load formed primarily by RLOAD

and COUT, as shown in Figure 5.

The Voltage Error Amplifier output (VC), provides a com‑

mand input to the VCCS. The full scale range of VC is 0.7V

(200mV to 900mV). With a full scale command on VC, the

LT3154 buck‑boost converter will generate an average 7A

of inductor current (typical) from the converter making

the transconductance gain 10A/V. As with peak current

mode control, the inner average current control loop

effectively turns the inductor into a current source over

the frequency range of interest, resulting in a frequency

response from the power stage that exhibits a single pole

(–20dB/decade) roll‑off. The output capacitor (COUT) and

load resistance (RLOAD) form a dominant low frequency

pole, where the effective series resistance of the output

capacitor and its capacitance form a zero, usually at a high

enough frequency to be ignored.

A potentially troublesome Right Half Plane Zero (RHPZ)

is also encountered if the converter is operated in boost

mode.TheRHPZcausesanincreaseingain,likeazero,but

a decrease in phase, like a pole. This can ultimately limit

the maximum converter bandwidth that can be achieved

with the LT3154. The RHPZ is not present when operating

in buck mode.

The overall open loop gain at DC is the product of the

following terms:

Voltage Error Amp Gain:gmVEA •RVEA =

110µs•5MΩ=550V/V(Fixed)

Voltage Divider Gain: VFB

VOUT

Current Loop Trans−Conductance:

gm =10A/V(Fixed)

LoadResistance (RLOAD)=

VOUT

ILOAD

The application dependent terms that affect the loop gain

include:

Output LoadPole (P1):=

(2πRLOAD •COUT)

Right Half Plane Zero (RHPZ):

VIN2 •RLOAD

VOUT2 •2π•L

Voltage Error Amplifier Compensation

(2Poles and1Zero)

The voltage amplifier’s frequency response is designed to

optimize the response for the overall loop. Measurement

of the power stage gain over line, load, component varia‑

tion, and frequency is strongly recommended prior to loop

design. The design parameters for compensation design

will focus on the series resistor and capacitors connected

from VC to GND (RC, CC and CHF). Being a buck‑boost

converter, the target loop crossover frequency for the

compensation design will be dictated by the highest boost

ratio and load current that is expected as this will result in

the lowest RHPZ frequency. The general goal is to set the

crossover frequency and provide sufficient phase boost

using the external compensation network.

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