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24LC256-E/P Datasheet(PDF) 4 Page - Microchip Technology

Part # 24LC256-E/P
Description  256K I2C Serial EEPROM
PDF  42 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

24LC256-E/P Datasheet(HTML) 4 Page - Microchip Technology

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24AA256/24LC256/24FC256
DS20001203W-page 4
 1998-2019 Microchip Technology Inc.
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
TA = -40°C to +85°C
Extended (E):
VCC = +1.7V to 5.5V
TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1FCLK
Clock Frequency
—
100
kHz
1.7V
 VCC  2.5V
—400
kHz
2.5V
 VCC  5.5V
—400
kHz
1.7V
 VCC  2.5V (24FC256)
—
1000
kHz
2.5V
 VCC  5.5V (24FC256)
2THIGH
Clock High Time
4000
—
ns
1.7V
 VCC  2.5V
600
—
ns
2.5V
 VCC  5.5V
600
—
ns
1.7V
 VCC  2.5V (24FC256)
500
—
ns
2.5V
 VCC  5.5V (24FC256)
3TLOW
Clock Low Time
4700
—
ns
1.7V
 VCC  2.5V
1300
—
ns
2.5V
 VCC  5.5V
1300
—
ns
1.7V
 VCC  2.5V (24FC256)
500
—
ns
2.5V
 VCC  5.5V (24FC256)
4TR
SDA and SCL Rise Time
—
1000
ns
1.7V
 VCC  2.5V (Note 1)
—
300
ns
2.5V
 VCC  5.5V (Note 1)
—
300
ns
1.7V
 VCC  5.5V (24FC256)
(Note 1)
5TF
SDA and SCL Fall Time
—
300
ns
All except 24FC256 (Note 1)
—
100
ns
1.7V
 VCC  5.5V (24FC256)
(Note 1)
6THD:STA Start Condition Hold Time
4000
—
ns
1.7V
 VCC  2.5V
600
—
ns
2.5V
 VCC  5.5V
600
—
ns
1.7V
 VCC  2.5V (24FC256)
250
—
ns
2.5V
 VCC  5.5V (24FC256)
7TSU:STA Start Condition Setup Time
4700
—
ns
1.7V
 VCC  2.5V
600
—
ns
2.5V
 VCC  5.5V
600
—
ns
1.7V
 VCC  2.5V (24FC256)
250
—
ns
2.5V
 VCC  5.5V (24FC256)
8THD:DAT Data Input Hold Time
0
—
ns
Note 2
9TSU:DAT Data Input Setup Time
250
—
ns
1.7V
 VCC  2.5V
100
—
ns
2.5V
 VCC  5.5V
100
—
ns
1.7V
 VCC  5.5V (24FC256)
10
TSU:STO Stop Condition Setup Time
4000
—
ns
1.7V
 VCC  2.5V
600
—
ns
2.5V
 VCC  5.5V
600
—
ns
1.7V
 VCC  2.5V (24FC256)
250
—
ns
2.5V
 VCC  5.5V (24FC256)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.



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