Philips Semiconductors

Product specification

74ALVT16823

2.5V/3.3V 18-bit bus-interface D-type flip-flop

with reset and enable (3-State)

1998 Jun 12

8

AC SETUP REQUIREMENTS (2.5V

"0.2V RANGE)

LIMITS

SYMBOL

PARAMETER

WAVEFORM

UNIT

MIN

TYP

Setup time, High or Low

nDx to nCP

3

1.0

1.8

0.5

1.3

ns

Hold time, High or Low

nDx to nCP

3

0.1

0.1

–1.4

–0.5

ns

nCP pulse width

High or Low

1

2.0

3.0

0.8

2.1

ns

Setup time, High or Low

nCE to nCP

3

1.0

0.5

0.2

–0.1

ns

Hold time, High or Low

nCE to nCP

3

1.0

1.0

0.2

–0.1

ns

nMR pulse width, Low

2

2.0

0.8

ns

Recovery time

nMR to nCP

2

2.0

1.3

ns

AC WAVEFORMS

The shaded areas indicate when the input is permitted to change for

predictable output performance.

SH00017

nCP

nQx

tw(H)

tw(L)

whichever

is less

0V

0V

Waveform 1. Propagation Delay, Clock Input to Output,

Clock Pulse Width, and Maximum Clock Frequency

nMR

nQx

tw(L)

nCP

SH00018

whichever

is less

0V

whichever

is less

0V

0V

Waveform 2. Master Reset Pulse WIdth, Master Reset to

Output Delay and Master Reset to Clock Recovery Time

th(H)

ts(H)

nCP

th(L)

ts(L)

nDx,

nCE

SH00019

whichever

is less

0V

whichever

is less

0V

Waveform 3. Data Setup and Hold Times

VOH–0.3V

VM

VM

VM

nQx

tPZH

tPHZ

nOE

0V

VOH

SH00020

whichever

is less

0V

Waveform 4. 3-State Output Enable Time to High Level

and Output Disable Time from High Level