EM78P813

8-bit OTP Micro-controller

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* This specification is subject to change without notice.

49

2004/8/19

(V1.6)

mode. When this bit is set to “0”, the Energy Detector works at low frequency mode. The difference between high

frequency and low frequency is as follows.

DEDPWR DEDCLK

ENPLL

Energy detector clock

Main CLK

0

X

X

X

Decision by ENPLL

1

0

0

32.768 KHz

Disable

1

0

1

32.768 KHz

Enable

1

1

0

3.5826 MHz

Enable

1

1

1

3.5826 MHz

Enable

PS. “X” means don’t care

Bit 3(CW_SMB) : Call Waiting / short message receiver switch

0

Short message mode select.

1

Call Waiting mode select. CAS tone accepted frequency range deviation is decided on CODE Option

Register bit 5 ( 1:for Europe and USA / 0:for China )

Bit 4 (WUEDD) : Wake-up control of Energy Detector (DED) output data

1/0

enable/disable

Bit 5 (EDGE) : Wake-up and interrupt trigging edge control of Energy Detector (DED) output

1/0

Falling edge trig. / Rising edge and Falling edge trig.

Bit 6(DEDD) : Output data of Differential Energy Detector (DED) If input signal from TIP/EGIN1 and RING/EGIN2 pin

to Differential Energy Detector is over the threshold level setting at IOCE PAGE 2 bit 0 (DEDTHD), the DED will

extract the zero-crossing pulse waveform corresponding to input signal.

Bit 7 (VRSEL) : Reference voltage VR selection bit for Comparator

0

VR = VDD

1

VR = 2.0V

When this bit is set to “0”, V2_0 ref. circuit will be powered off. 2.0V ref. circuit is only powered on when this

bit and RA page2 bit 7(CMPEN) are all set to “1”.

IOCF Interrupt Mask Register2

7

6

5

4

3

2

1

0

RBF/STD FSK/CW

0

UART

DED

CNT2

CNT1

TCC

Bit 0~Bit 4, Bit6~Bit7 : Interrupt enable bits.

0/1

disable interrupt/enable interrupt

Bit4: Undefined register. This bit must keep to 0.