Advanced Clock Drivers Device Data

Freescale Semiconductor

15

MPC9773

Offset) Test Reference

Figure 19. Output Duty Cycle (DC)

The pin-to-pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

The time from the PLL controlled edge to the non controlled edge,

divided by the time between PLL controlled edges, expressed as

a percentage

GND

GND

GND

GND

GND

CCLKx

FB_IN

CCLKx

FB_IN

sample of cycles

Figure 20. I/O Jitter

Figure 21. Cycle-to-Cycle Jitter

Figure 22. Period Jitter

The variation in cycle time of a signal between adjacent cycles, over a random

sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over a

random sample of cycles

2.4

0.55

Figure 23. Output Transition Time Test Reference