1

• Fabricated on Honeywell’s Radiation Hardened

– 0.65

µm

– 0.55

µm

• Array Sizes from 40K to 390K Available Gates (Raw)

• HX2000 Supports 5V Core Operation

• HX2000r Supports 3.3V Core Operation

• HX2000r Supports Mixed Voltage I/O Buffers

• TTL (5V) or CMOS (5V/3.3V) Compatible I/O

• Configurable Multi-Port Gate Array SRAM

• Single or Dual Port Custom SRAM Drop-In Capability

• Supports Chip Level Power Down for Cold Sparing

• Supports System Speeds Beyond 100 MHz

FEATURES

RICMOS™ SOI GATE ARRAYS

HX2000

HX2000r

FAMILY

The HX2000 and HX2000r gate arrays are performance

oriented sea-of-transistor arrays, fabricated on

Honeywell’s RICMOS™ IV Silicon On Insulator (SOI) pro-

cess. The HX2000 arrays are for 5V designs only. The

HX2000r arrays support 5V and 3.3V operation. High

density is achieved with the standard 3-layer metal or

optional 4-layer metal process, providing up to 290,000

usable gates. The high density and performance charac-

teristics of the RICMOS (Radiation Insensitive CMOS) SOI

process make possible device operation beyond 100 MHz

over the full military temperature range, even after expo-

Flops have been designed for a Soft Error Rate (SER) of

case environment.

Each HX2000/HX2000r design is founded on our proven

RICMOS ASIC library of SSI and MSI logic elements,

configurable RAM cells, and selectable I/O pads. The gate

arrays feature a global clock network capable of handling

multiple clock signals with low clock skew between regis-

ters. This family is fully compatible with Honeywell’s high

reliability screening procedures and consistent with QML

Class Q and V requirements.

Designers can choose from a wide variety of I/O types.

Output buffer options include 8 drive strengths, CMOS/TTL

levels, IEEE 1149.1 boundary scan, pull-up/pull-down re-

sistors, and three-state capability. Input buffers can be

selected for CMOS/TTL/Schmitt trigger levels, IEEE

1149.1 boundary scan and pull-up/pull-down resistors.

Bi-directional buffers are also available.

An important feature of HX2000r is the dual voltage I/O

capability in which the designer has complete flexibility in

terms of placement of I/O buffers. This feature allows

adjacent I/O buffers with different supply voltages.

The HX2000/HX2000r families provide options for config-

urable multi-port SRAMs. Word widths can be selected in

single bit increments. A variety of SRAM read and write port

options are available to serve most applications. Custom

drop-in macrocells can also be implemented to further

increase chip density. Word widths can be selected in two

bit increments. Single port and two port options are avail-

able.

The HX2000/HX2000r families have a special feature to

allow a chip level power down mode, in which the associ-

ated buses connected to the chip can remain active. This

GENERAL DESCRIPTION

• Total Dose Hardness

• Dose Rate Upset Hardness:

Option Available for:

• Dose Rate Survivability

• Soft Error Rate

• No Latchup

*Projected

Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com