Philips Semiconductors

Product specification

74F373/74F374

Latch/flip-flop

December 5, 1994

7

AC SETUP REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

TEST

UNIT

CONDITION

MIN

TYP

MAX

MIN

MAX

Setup time, high or low level

Dn to E

Waveform 4

0

1.0

0

1.0

ns

Hold time, high or low level

Dn to E

74F373

Waveform 4

3.0

3.0

3.0

3.0

ns

E Pulse width, high

Waveform 1

3.5

4.0

ns

Setup time, high or low level

Dn to CP

Waveform 5

2.0

2.0

2.0

2.0

ns

Hold time, high or low level

Dn to CP

74F374

Waveform 5

0

0

0

0

ns

CP Pulse width,

high or low

Waveform 5

3.5

4.0

3.5

4.0

ns

AC WAVEFORMS

The shaded areas indicate when the input is permitted to change for

predictable output performance.

CP VM

VM

VM

tw(H)

1/fmax

VM

VM

tPHL

tw(L)

tPLH

Qn

SF00258

Waveform 1. Propagation delay for clock input to output,

clock pulse widths, and maximum clock frequency

tPHL

EVM

VM

VM

tw(H)

VM

VM

Qn

tPLH

SF00259

Waveform 2. Propagation delay for enable to output

and enable pulse width

Dn

VM

VM

VM

VM

tPHL

tPLH

Qn

SF00260

Waveform 3. Propagation delay for data to output

VM

VM

VM

VM

VM

VM

tsu(L)

th(L)

tsu(H)

th(H)

E

Dn

SF00261

Waveform 4. Data setup time and hold times