Philips Semiconductors

Product specification

74F50109

Synchronizing dual J–K positive edge-triggered

flip-flop with metastable immune characteristics

September 14, 1990

8

AC WAVEFORMS

VM

VM

CPn

VM

VM

VM

VM

VM

VM

tsu(H)

th(H)

Jn, Kn

Qn

VM

tw(H)

1/fmax

tsu(L)

th(L)

VM

VM

tPLH

Qn

tw(L)

tPHL

tPHL

tPLH

SF00139

Waveform 1. Propagation delay for data to output, data

setup time and hold times, and clock

width, and maximum clock frequency

SDn or RDn

CPn

SF00603

Waveform 3. Recovery time for set or reset to output

VM

VM

RDn

VM

Qn

VM

VM

VM

tPLH

Qn

tw(L)

tPHL

tPHL

tPLH

SDn

VM

VM

tw(L)

SF00050

Waveform 2. Propagation delay for set and reset to output,

set and reset pulse width

Qn, Qn

VM

VM

tsk(o)

Qn, Qn

SF00590

Waveform 4. Output skew

NOTES:

The shaded areas indicate when the input is permitted to change for

predictable output performance.

TEST CIRCUIT AND WAVEFORM

tw

90%

VM

10%

90%

VM

10%

90%

VM

10%

90%

VM

10%

NEGATIVE

PULSE

POSITIVE

PULSE

tw

AMP (V)

0V

0V

tTHL (tf )

INPUT PULSE REQUIREMENTS

rep. rate

1MHz

500ns

2.5ns

2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

RL

CL

RT

VIN

VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

see AC ELECTRICAL CHARACTERISTICS for value.

see AC ELECTRICAL CHARACTERISTICS for value.

pulse generators.

tTHL (tf )

tTLH (tr )

tTLH (tr )

AMP (V)

amplitude

3.0V

1.5V

SF00006