VNQ7003SY datasheet(53/102 Pages) STMICROELECTRONICS

53 / 102 page

DS11059 Rev 8

53/102

VNQ7003SY

Diagnostic

5.11

Address 0x34h — Generic Status Register (GENSR)

5.12

Address 0x3Fh — Configuration Register (CONFIG)

Table 49. GENSR — Generic Status Register

Bit

Name

Access

Reset

Content

VCCUV

VCC undervoltage detection,

Active High: this bit is related to the VCC undervoltage detection and is

real time, means that it is set when VCC < VUSD and it is automatically

reset as soon as VCC > VUSD + VUSDHYST.

This bit sets the Global Error Flag of the GSB.

6RST

R/C

Active High: this bit is high in case of chip reset (hardware reset due to a

loss of VREG supply or software reset).

This bit is set until a Read and Clear Command is performed.

SPIE

R/C

Active High: this bit is set at end of Communication in case of wrong

number of clock cycles during a communication frame or invalid bus

condition or SDI stuck at High or Low conditions.

This bit is set until a Read and Clear is performed.

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Reserved

—

Table 50. CONFIG — Configuration Register

Bit

Name

Access

Reset

Content

Reserved

—

Reserved

—

Reserved

—

Reserved

VDSMASK3

R/W

Masks the contribution of the VDS status bit in the channel feedback

status register and Global Status Byte

For channel 3

1: VDS bit is masked

0: VDS bit not masked

VDSMASK2

R/W

Masks the contribution of the VDS status bit in the channel feedback

status register and Global Status Byte

For channel 2

1: VDS bit is masked

0: VDS bit not masked

VDSMASK1

R/W

Masks the contribution of the VDS status bit in the channel feedback

status register and Global Status Byte

For channel 1

1: VDS bit is masked

0: VDS bit not masked

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