Philips Semiconductors

Product specification

74F821/822/823/824/825/826

Bus interface registers

1996 Jan 05

7

LOGIC DIAGRAM FOR 74F822

GND = Pin 12

D

CP Q

Q0

23

D

CP Q

Q1

22

D

CP Q

Q2

21

D

CP Q

Q3

20

D

CP Q

Q4

19

D

CP Q

Q5

18

D

CP Q

Q6

17

D

CP Q

Q7

16

D

CP Q

Q8

15

D

CP Q

Q9

14

13

CP

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6

8

D7

9

D8

10

D9

11

SF00501

1

OE

FUNCTION TABLE FOR 74F821 AND 74F822

INPUTS

OUTPUTS

INPUTS

74F821

74F822

OPERATING MODE

OE

CP

Dn

Q

Q

L

↑

l

L

H

Load and read data

L

↑

h

H

L

Load and read data

L

↑

X

NC

NC

Hold

H

X

X

Z

Z

High impedance

H = High-voltage level

h

= High state must be present one setup time before the low-to-high clock transition

L

= Low-voltage level

l

= Low state must be present one setup time before the low-to-high clock transition

NC= No change

X = Don’t care

Z = High impedance “off” state

↑ = Low-to-high clock transition

↑ = Not low-to-high clock transition

LOGIC DIAGRAM FOR 74F823

GND = Pin 12

D0

D

R

Q

Q0

2

23

D1

Q1

3

22

D2

Q2

4

21

D3

Q3

5

20

D4

Q4

6

19

D5

Q5

7

18

D6

Q6

8

17

D7

Q7

9

16

D8

Q8

10

15

11

MR

CP

CE

14

SF00502A

CP

13

OE

1

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP