Page 4 of 5

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Rev 1.0

16/07/2021

CMOS High Voltage Logic – MM74C14

4. Not production tested in die form, characterized by chip design.

5. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

Figure 1 – Transfer Characteristics

Figure 2 – Guaranteed Trip Point Range

DC Electrical Characteristics T

A = -40 to +85°C unless otherwise stated

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

CMOS/LPTTL INTERFACE

Logical “1” Input Voltage

VIN(1)

VCC = 5V

4.3

-

-

V

Logical “0” Input Voltage

VIN(0)

VCC = 5V

-

-

0.7

V

Logical “1” Output Voltage

VOUT(1)

VCC= 4.75V,

IO= -360µA

2.4

-

-

V

Logical “0” Output Voltage

VOUT(0)

VCC =4.75V,

IO = 360µA

-

-

0.4

V

OUTPUT DRIVE CURRENT TA = 25°C

VCC = 5V, VOUT = 0V

-1.75

-3.3

-

mA

Output Source Current

(P-Channel)

ISOURCE

VCC = 10V, VOUT = 0V

-8.0

-15

-

mA

VCC = 5V, VOUT = VCC

1.75

3.6

-

mA

Output Source Current

(N-Channel)

ISINK

VCC = 10V, VOUT = VCC

8.0

16

-

mA

DYNAMIC ELECTRICAL CHARACTERISTICS

4 T

A = 25°C, CL = 50pF unless otherwise stated

VCC = 5V

-

220

400

ns

Propagation Delay

from Input to Output

tPD0,

tPD1

VCC = 10V

-

80

200

ns

Input Capacitance

CIN

Any Input

-

5.0

-

pF

Power Dissipation Capacitance

5

CPD

Per Gate

-

20

-

pF

Typical Characteristics