5.2.2

Current address read

For the current address read operation, following a start condition, the bus master only sends a device select

code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal

address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition,

as shown in Figure 9, without acknowledging the byte.

5.2.3

Sequential read

This operation can be used after a current address read or a random address read. The bus master does

acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the

next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and

must generate a stop condition, as shown in Figure 9.

The output data comes from consecutive addresses, with the internal address counter automatically incremented

after each byte output. After the last memory address, the address counter "rolls-over", and the device continues

to output data from memory address 00h.

M24C16-W M24C16-R M24C16-F

Read operations

DS9194 - Rev 11

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