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M95128-DF Datasheet(PDF) 21 Page - STMicroelectronics

Part # M95128-DF
Description  128-Kbit serial SPI bus EEPROM with high-speed clock
PDF  48 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95128-DF Datasheet(HTML) 21 Page - STMicroelectronics

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6.8
Write Identification page (available only in M95128-D devices)
The Identification page (64 bytes) is an additional page that can be written and (later) permanently locked in
Read-only mode.
Writing this page is achieved with the Write Identification page instruction (see Table 4. Instruction set). The Chip
select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are
then shifted in on Serial data input (D). Address bit A10 must be 0, upper address bits are Don't care, the lower
address bits [A5:A0] define the byte address within the Identification page. The instruction sequence is shown in
Figure 16. Write Identification page sequence.
Figure 16. Write Identification page sequence
C
D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
High impedance
Instruction
16-bit address
0
7
6
5
4
3
2
0
1
Data byte
31
6.9
Read Lock status (available only in M95128-D devices)
The Read Lock status instruction (see Table 4. Instruction set) is used to check whether the Identification page is
locked or not in Read-only mode. The Read Lock status sequence is defined with the Chip select (S) first driven
low. The bits of the instruction byte and address bytes are then shifted in on Serial data input (D). Address bit A10
must be 1, all other address bits are Don't Care. The Lock bit is the LSB (least significant bit) of the byte read on
Serial data output (Q). It is at “1” when the lock is active and at “0” when the lock is not active. If Chip select (S)
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by driving Chip select
(S) high.
The instruction sequence is shown in Figure 17. Read Lock status sequence.
Figure 17. Read Lock status sequence
C
D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
7
6
5
4
3
1
7
0
High impedance
Data Out 1
Instruction
16-bit address
0
MSB
MSB
2
31
Data Out 2
M95128-W M95128-R M95128-DF
Write Identification page (available only in M95128-D devices)
DS1356 - Rev 20
page 21/48



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