RHFL4913ESY151 datasheet(13/32 Pages) STMICROELECTRONICS

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RHFL4913XX15

Radiation performance

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Table 8: Test configuration

Test mode

Test configuration

SET

Configuration 1

(47 μF+100 nF set of capacitors in each output port):

- CIN1

= 100 μF tantalum, ESR < 30 mΩ

- COUT1 = COUT2 =

47 μF tantalum, < 30 mΩ

- CIN2 = COUT4 = COUT5 = 100 nF polyester(1)

- Cbyp = 10 nF polyester(1)

- Risc

= 40 kΩ (to achieve 2 A current limit)

Configuration 2

- CIN1 = COUT1

= 220 μF tantalum, ESR < 30 mΩ

- COUT2 = not connected

- CIN2= COUT4 = 100 nF polyester (1)

- COUT5 = not connected

- Cbyp = 10 nF polyester (1)

- Risc

= 40 kΩ (to achieve 2 A current limit)

SEL

SEL configuration

- CIN1

= 100 μF tantalum, ESR < 30 mΩ

- COUT1 = COUT2

= 47 μF tantalum, ESR < 30 mΩ

- CIN2 = COUT4 = COUT5 = 100 nF polyester (1)

- Cbyp = 10 nF polyester (1)

- Risc

= 40 kΩ (2 A current limit)

Notes:

(1)Order code: CDR04BX104AKWS, manufactured by AVX.

5.3

Guidelines for SET mitigation

This section provides a detailed description of possible solutions, which protect the load

against the SET. In this respect, there are two main areas of intervention: ground

connection and external component selection.

5.3.1

Ground connections

To achieve the best performance of output voltage accuracy, noise immunity and

robustness against single event effects, a proper PCB layout has to be developed, by

following below indications.

According to qualitative simulations of single event, some very short SET (i.e. those having

duration within 100 ns range) are strongly dependent on the stray inductances versus

GND. The best solution to reduce the parasitic inductance is the adoption of a GND plane

(with separate power and sense paths where possible). By minimizing the stray GND

impedance, a better control of the SET amplitude (near to the load) can be achieved.

If this solution is not applicable, a star-bus topology could be used, where the PCB

reference GND connection is close to the GND pin of the regulator.

To achieve a good GND sense, the following rules have to be met:



The regulator GND pin and load GND node have to be connected to the sense and

power GND traces on the PCB , using vias to minimize the path



An array of multiple via structures works better if compared to a single via



GND connectors/plugs: separate plugs have to be used for power supply and testing

probes



Input/output capacitor GND terminals have to be connected to GND sense on PCB

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