74HC670 datasheet(8/9 Pages) PHILIPS

8 / 9 page

December 1990

Philips Semiconductors

Product speciﬁcation

4 x 4 register ﬁle; 3-state

74HC/HCT670

AC WAVEFORMS

Fig.6

Waveforms showing the read address input

(RA, RB) to output (Qn) propagation delays

and output transition times.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.7

Waveforms showing the write enable input

(WE) and data input (Dn) to output (Qn)

propagation delays, and the write enable

pulse width.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.8

Waveforms showing the write address input (WA, WB) and data input (Dn) to write enable (WE) set-up,

hold and latch times.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

The shaded areas indicate when the input is permitted

to change for predictable output performance.

The time allowed for the internal output of the latch to

assume the state of the new data (tlatch) is important

only when attempting to read from a location

immediately after that location has received new data.

This parameter is measured from the falling edge of

WE to the rising edge of RA or RB, RE must be LOW.

74HC670 Datasheet(PDF) 8 Page - NXP Semiconductors