MCP2518FD datasheet(50/96 Pages) MICROCHIP

50 / 96 page

MCP2518FD

DS20006027A-page 50

 2019 Microchip Technology Inc.

bit 10

FRESET: FIFO Reset bit( 3)

1 = FIFO will be reset when bit is set; cleared by hardware when FIFO was reset. User should wait

until this bit is clear before taking any action.

0 = No effect

bit 9

TXREQ: Message Send Request bit( 2)

1 = Requests sending a message; the bit will automatically clear when all the messages queued in

the TXQ are successfully sent.

0 = Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

bit 8

UINC: Increment Head bit

When this bit is set, the FIFO head will increment by a single message.

bit 7

TXEN: TX Enable

1 = Transmit Message Queue. This bit always reads as ‘1’.

bit 6-5

Unimplemented: Read as ‘0’

bit 4

TXATIE: Transmit Attempts Exhausted Interrupt Enable bit

1 = Enable interrupt

0 = Disable interrupt

bit 3

Unimplemented: Read as ‘0’

bit 2

TXQEIE: Transmit Queue Empty Interrupt Enable bit

1 = Interrupt enabled for TXQ empty

0 = Interrupt disabled for TXQ empty

bit 1

Unimplemented: Read as ‘0’

bit 0

TXQNIE: Transmit Queue Not Full Interrupt Enable bit

1 = Interrupt enabled for TXQ not full

0 = Interrupt disabled for TXQ not full

CiTXQCON – TRANSMIT QUEUE CONTROL REGISTER (CONTINUED)

Note 1:

These bits can only be modified in Configuration mode.

This bit is updated when a message completes (or aborts) or when the FIFO is reset.

FRESET is set while in Configuration mode and is automatically cleared in Normal mode.

MCP2518FD Datasheet(PDF) 50 Page - Microchip Technology

MCP2518FD Datasheet(HTML) 50 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL