M25PE80 datasheet(39/61 Pages) STMICROELECTRONICS

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M25PE80

Instructions

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6.13

SubSector Erase (SSE)

Note:

The SubSector Erase (SSE) instruction is decoded only in the M25PE80 in the T9HX

process (see Important note on page 6).

The SubSector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector.

Before it can be accepted, a Write Enable (WREN) instruction must previously have been

executed. After the Write Enable (WREN) instruction has been decoded, the device sets the

Write Enable Latch (WEL).

The SubSector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, and three address Bytes on Serial Data Input (D). Any address inside

the SubSector (see Table 5) is a valid address for the SubSector Erase (SE) instruction.

Chip Select (S) must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 20.

Chip Select (S) must be driven High after the eighth bit of the last address Byte has been

latched in, otherwise the SubSector Erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed SubSector Erase cycle (whose duration is tSSE) is

initiated. While the SubSector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed SubSector Erase cycle, and is 0 when it is completed. At some

unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.

A SubSector Erase (SSE) instruction applied to a subsector that contains a page that is

Hardware or software Protected is not executed.

Any SubSector Erase (SSE) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

If Reset (Reset) is driven Low while a SubSector Erase (SSE) cycle is in progress, the

SubSector Erase cycle is interrupted and data may not be erased correctly (see Table 15:

Device status after a Reset Low pulse). On Reset going Low, the device enters the Reset

mode and a time of tRHSL is then required before the device can be re-selected by driving

Chip Select (S) Low. For the value of tRHSL see Table 24: Timings after a Reset Low pulse in

Section 11: DC and AC parameters.

Figure 19.

SubSector Erase (SSE) instruction sequence

Address bits A23 to A20 are Don’t Care.

24 Bit Address

AI12356

3456789

29 30 31

Instruction

23 22

MSB

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