M24256-B datasheet(4/19 Pages) STMICROELECTRONICS

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M24256-B, M24128-B

4/19

cycle) the SDA and SCL lines for a START condi-

tion, and will not respond unless one is given.

Stop Condition

STOP is identified by a low to high transition of the

SDA line while the clock SCL is stable in the high

state. A STOP condition terminates communica-

tion between the memory device and the bus mas-

ter. A STOP condition at the end of a Read

command, after (and only after) a NoAck, forces

the memory device into its standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

Acknowledge Bit (ACK)

An acknowledge signal is used to indicate a suc-

cessful byte transfer. The bus transmitter, whether

it be master or slave, releases the SDA bus after

sending eight bits of data. During the 9th clock

pulse period, the receiver pulls the SDA bus low to

acknowledge the receipt of the eight data bits.

Data Input

During data input, the memory device samples the

SDA bus signal on the rising edge of the clock,

SCL. For correct device operation, the SDA signal

must be stable during the clock low-to-high transi-

tion, and the data must change

only when the SCL

line is low.

Memory Addressing

To start communication between the bus master

and the slave memory, the master must initiate a

START condition. Following this, the master sends

the 8-bit byte, shown in Table 3, on the SDA bus

line (most significant bit first). This consists of the

7-bit Device Select Code, and the 1-bit Read/Write

Designator (RW). The Device Select Code is fur-

ther subdivided into: a 4-bit Device Type Identifier,

and a 3-bit Chip Enable “Address” (E2, E1, E0).

To address the memory array, the 4-bit Device

Type Identifier is 1010b.

Figure 4. I2C Bus Protocol

SCL

SDA

SCL

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

MSB

ACK

START

CONDITION

SCL

123

MSB

ACK

STOP

CONDITION

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