Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1997 Dec 05

14

AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE

SYMBOL

PARAMETER

INPUT

OUTPUT

SCL TIMING CHARACTERISTICS

tHD;STA

START condition hold time

≥ 14 tCLCL

> 4.0

µs1

tLOW

SCL LOW time

≥ 16 tCLCL

> 4.7

µs1

tHIGH

SCL HIGH time

≥ 14 tCLCL

> 4.0

µs1

tRC

SCL rise time

≤ 1

µs

– 2

tFC

SCL fall time

≤ 0.3

µs

< 0.3

µs3

SDA TIMING CHARACTERISTICS

tSU;DAT1

Data set-up time

≥ 250ns

> 20 tCLCL – tRD

tSU;DAT2

SDA set-up time (before rep. START cond.)

≥ 250ns

> 1

µs1

tSU;DAT3

SDA set-up time (before STOP cond.)

≥ 250ns

> 8 tCLCL

tHD;DAT

Data hold time

≥ 0ns

> 8 tCLCL – tFC

tSU;STA

Repeated START set-up time

≥ 14 tCLCL

> 4.7

µs1

tSU;STO

STOP condition set-up time

≥ 14 tCLCL

> 4.0

µs1

tBUF

Bus free time

≥ 14 tCLCL

> 4.7

µs1

tRD

SDA rise time

≤ 1

µs

– 2

tFD

SDA fall time

≤ 0.3

µs

< 0.3

µs3

NOTES:

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1

µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and

SCL = 400pF.

4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 63ns (42ns) < tCLCL < 285ns (16MHz (24MHz) > fOSC > 3.5MHz) the SI01

interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.

TIMING SIO1 (I2C) INTERFACE

tRD

tSU;STA

tBUF

tSU; STO

0.7 VDD

0.3 VDD

0.7 VDD

0.3 VDD

tFD

tRC

tFC

tHIGH

tLOW

tHD;STA

tSU;DAT1

tHD;DAT

tSU;DAT2

tSU;DAT3

START condition

repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

STOP condition

START or repeated START condition