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June 17, 2005

IDT 89TSF552

*Notice: The information in this document is subject to change without notice

However, if appropriate current limiting techniques (e.g., series resistors) are employed and the 2.5V and 1.5V power supplies ramp down soon

after the 1.8V core power supply (within about 50 ms), the system designer can safely ignore this recommendation.

PLL Power-Up Initialization

PLL inputs into the 89TSF552, from an external device such as the ZBus bridge in IDT’s reference system, require a special initialization

sequence. Figure 9 shows the initialization sequence.

PLL initialization is necessary only at power-up. If the PLLs fail to lock, repeatedly assert PLL_RST until they do.

Note: The 89TSF552 must be reset after PLL initialization. Hold RESET_N low for at least 16 clocks (SYS_CLK) after PLL initialization

completes.

Figure 9 PLL Power-Up Initialization for the 89TSF552

Device Reset

It is possible to reset the entire 89TSF552 device except for the PLL. To reset the device without being required to re-initialize the PLL, assert the

RESET_N pin (low) for at least 16 clocks (SYS_CLK) and then deassert it.

Pin List I/O Description

The 89TSF552 Pin List on page 19 uses the following I/O notations:

I

Input

O

Output

B

Bidirectional

PPower

DNC

Do not connect

RPD

Reserved, pulldwn. Pin must be connected to VSS through a 300 - 1K

Ω resistor.

RPU

Reserved, pullup. Pin is connected to VDD_IO (3.3V) through a 1K - 10K

Ω resistor.

PLL_DIV_RST_N

1 µs min

TACQUIRE, 15 µs min

PLL_SYS_LCK

10 ns min

PLL_RST

Repeat if necessary until

lock is achieved.

RESET_N

TRESET, 16 clocks min

Power Supplies

Clock

clock present and stable

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