STM32G0C1NET6X datasheet(35/159 Pages) STMICROELECTRONICS

35 / 159 page

DS13564 Rev 4

35/159

STM32G0C1xC/xE

Functional overview

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

The LPUART interface can be served by the DMA controller.

3.25

Serial peripheral interface (SPI)

The device contains three SPIs running at up to 32 Mbits/s in master and slave modes. It

supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight

master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI

peripherals support NSS pulse mode, TI mode and hardware CRC calculation.

The SPI peripherals can be served by the DMA controller.

The I2S interface mode of the SPI peripheral (if supported, see the following table) supports

four different audio standards can operate as master or slave, in half-duplex communication

mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data

resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to

192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master

mode, it can output a clock for an external audio component at 256 times the sampling

frequency.

3.26

Universal serial bus device (USB) and host (USBH)

The devices embed a USB controller with full-speed USB device and host functionality

compliant with the USB specification version 2.0. The internal USB PHY supports USB FS

signaling, embedded DP pull-up and also battery charging detection according to Battery

Charging Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s)

function interface with added support for USB 2.0 Link Power Management. It has software-

configurable endpoint setting with packet memory up to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock that is generated from the internal main PLL (the clock

source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic

trimming mode. The synchronization for this oscillator can be taken from the USB data

stream itself (SOF signalization) which allows crystal less operation.

Table 10. SPI/I2S implementation

SPI features(1)

1. X = supported.

SPI1

SPI2

SPI3

Hardware CRC calculation

Rx/Tx FIFO

NSS pulse mode

I2S mode

TI mode

STM32G0C1NET6X Datasheet(PDF) 35 Page - STMicroelectronics

STM32G0C1NET6X Datasheet(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL