32

AT25DF011

DS-25DF011–032I–03/2022

14.

Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) will be in a high

impedance state, and a high-to-low transition on the CSB pin will be required to start a valid instruction. The SPI mode

(Mode 3 or Mode 0) will be automatically selected on every falling edge of CSB by sampling the inactive clock state.

14.1 Power-Up/Power-Down Voltage and Timing Requirements

During power-up, the device must not be READ for at least the minimum tVCSL time after the supply voltage reaches the

minimum VPOR level (VPOR min). While the device is being powered-up, the internal Power-On Reset (POR) circuitry

keeps the device in a reset mode until the supply voltage rises above the minimum Vcc. During this time, all operations

are disabled and the device will not respond to any commands.

If the first operation to the device after power-up will be a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum VCC level and an internal device delay has elapsed. This delay will

be a maximum time of tPUW. After the tPUW time, the device will be in the standby mode if CSB is at logic high or active

mode if CSB is at logic low. For the case of Power-down then Power-up operation, or if a power interruption occurs (such

that VCC drops below VPOR max), the Vcc of the Flash device must be maintained below VPWD for at least the minimum

specified TPWD time. This is to ensure the Flash device will reset properly after a power interruption.

Table 14-1. Voltage and Timing Requirements for Power-Up/Power-Down

Figure 14-1. Power-Up Timing

Symbol

Parameter

Min

Max

Units

VPWD

(1)

1.

Not 100% tested (value guaranteed by design and characterization).

VCC for device initialization

1.0

V

tPWD

(1)

Minimum duration for device initialization

300

µs

tVCSL

Minimum VCC to chip select low time for Read command

70

µs

tVR

(1)

VCC rise time

1

500000

µs/V

VPOR

Power on reset voltage

1.45

1.6

V

tPUW

Power up delay time before Program or Erase is allowed

3

ms

VCC

V

POR max

Max V

PWD

Time

t

PWD

t

PUW

Full Operation Permitted

t

VR

t

VCSL

Read Operation

Permitted