CD40105BMS datasheet(9/10 Pages) RENESAS

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CD40105BMS

FN3353 Rev 0.00

Page 9 of 10

December 1992

FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM

FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG

FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS

CONTROL LOGIC

4 x 16

DATA

INPUT

BUFFERS

OUTPUT

BUFFERS

3-STATE

CONTROL

DATA-IN

READY (DIR)

SHIFT IN (SI)

MASTER

RESET (MR)

DATA-OUT

READY (DOR)

SHIFT OUT (SO)

DOR

DIR MR SO

DOR

DIR MR SO

1 1

MASTER

RESET

SHIFT IN

(DATA VALID)

SHIFT OUT

INPUT READY

(CLEAR OUT)

OUTPUT READY

(CLEAR OUT)

DATA IN (Dn)

3-STATE

(OUTPUT

ENABLE)

DATA OUT

***

(UNKNOWN)

SHIFT-OUT PULSES

HAVE NO EFFECT

 2s

SHIFT-IN PULSES

HAVE NO EFFECT

 2s

HIGH

INVALID

*AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16

**AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1

***DATA VALID goes to high level in advance of the DATA OUT

and 20ns at VDD = 15V for CL = 50pF and TA = 25oC

by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V,

INPUTS

OUTPUTS

INPUTS

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