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CD4011BMS Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # CD4011BMS
Description  CMOS NAND Gates
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

CD4011BMS Datasheet(HTML) 9 Page - Renesas Technology Corp

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CD4011BMS, CD4012BMS, CD4023BMS
FN3079 Rev 0.00
Page 9 of 9
November 1994
Chip Dimensions and Pad Layouts
FIGURE 7. TYPICAL PROPAGATION DELAY TIME PER GATE
AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
CD4011BMSH
CD4012BMSH
CD4023BMSH
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
10V
15V
SUPPLY VOLTAGE (VDD) = 5V
LOAD CAPACITANCE (CL) (pF)
200
175
150
125
100
75
50
25
0
10
20
30
40
50
60
70
80
90
100
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
40
6080100
20
0
50
100
150
200
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11k
Å 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6k
Å, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches



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