January 22, 2020

11

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

87016I DATASHEET

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1

shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and

R2/R1 = 0.609.

Figure 1. Single-Ended Signal Driving Differential Input

Recommendations for Unused Input and Output Pins

Inputs

CLK/CLK Inputs

For applications not requiring the use of the differential input, both

CLK and CLK can be left floating. Though not required, but for

additional protection, a 1k

 resistor can be tied from CLK to ground.

CLK Input

For applications not requiring the use of a clock input, it can be left

floating. Though not required, but for additional protection, a 1k



resistor can be tied from the CLK input to ground.

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1k

 resistor can be used.

Outputs

LVCMOS Outputs

All unused LVCMOS output can be left floating. There should be no

trace attached.

V_REF

Single Ended Clock Input

VDD

CLK

nCLK

R1

1K

C1

0.1u

R2

1K