P80C31UFAA datasheet(17/38 Pages) PHILIPS

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Philips Semiconductors

Product specification

80C51/87C51/80C31

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),

low power, high speed (33 MHz)

2000 Jan 20

Interrupt Priority Structure

The 8XC51 and 80C31 only have a 6-source four-level interrupt

structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)

The IPH (Interrupt Priority High) register that makes the four-level

interrupt structure possible. The IPH is located at SFR address B7H.

The structure of the IPH register and a description of its bits is

shown in Figure 12.

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

INTERRUPT PRIORITY LEVEL

Level 0 (lowest priority)

Level 1

Level 2

Level 3 (highest priority)

An interrupt will be serviced as long as an interrupt of equal or

higher priority is not already being serviced. If an interrupt of equal

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

interrupt is being serviced, it will be stopped and the new interrupt

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

IE0

N (L)1

Y (T)2

03H

TP0

0BH

IE1

N (L)

Y (T)

13H

TF1

1BH

RI, TI

23H

TF2, EXF2

2BH

NOTES:

1. L = Level activated

2. T = Transition activated

EX0

IE (0A8H)

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables it.

BIT

SYMBOL

FUNCTION

IE.7

Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

enabled or disabled by setting or clearing its enable bit.

IE.6

—

Not implemented. Reserved for future use.

IE.5

ET2

Timer 2 interrupt enable bit.

IE.4

Serial Port interrupt enable bit.

IE.3

ET1

Timer 1 interrupt enable bit.

IE.2

EX1

External interrupt 1 enable bit.

IE.1

ET0

Timer 0 interrupt enable bit.

IE.0

EX0

External interrupt 0 enable bit.

SU00571

ET0

EX1

ET1

ET2

—

Figure 10. IE Registers

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