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HIP4080IP Datasheet(PDF) 18 Page - Renesas Technology Corp |
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HIP4080IP Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 21 page  HIP4080 FN3178 Rev 11.00 Page 18 of 21 February, 2003 Supplemental Information for HIP4080 and HIP4081 Power-Up Application The HIP4080 and HIP4081 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers. If not addressed in the application, the H-bridge power MOSFETs may be exposed to shoot-through current, possibly leading to MOSFET failure. Following the instructions below will result in reliable start-up. HIP4081 The HIP4081 has four inputs, one for each output. Outputs ALO and BLO are directly controlled by input ALI and BLI. By holding ALI and BLI low during start-up no shoot-through conditions can occur. To set the latches to the upper drivers such that the driver outputs, AHO and BHO, are off, the DIS pin must be toggled from low to high after power is applied. This is accomplished with a simple resistor divider, as shown below in Figure 36. As the VDD/VCC supply ramps from zero up, the DIS voltage is below its input threshold of 1.7V due to the R1/R2 resistor divider. When VDD/VCC exceeds approximately 9V to 10V, DIS becomes greater than the input threshold and the chip disables all outputs. It is critical that ALI and BLI be held low prior to DIS reaching its threshold level of 1.7V while VDD/VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low. HIP4080 The HIP4080 does not have an input protocol like the HIP4081 that keeps both lower power MOSFETs off other than through the DIS pin. IN+ and IN- are inputs to a comparator that control the bridge in such a way that only one of the lower power devices is on at a time, assuming DIS is low. However, keeping both lower MOSFETs off can be accomplished by controlling the lower turn-on delay pin, LDEL, while the chip is enabled, as shown in Figure 37. Pulling LDEL to VDD will indefinitely delay the lower turn-on delays through the input comparator and will keep the lower MOSFETs off. With the lower MOSFETs off and the chip enabled, i.e., DIS = low, IN+ or IN- can be switched through a full cycle, properly setting the upper driver outputs. Once this is accomplished, LDEL is released to its normal operating point. It is critical that IN+/IN- switch a full cycle while LDEL is held high, to avoid shoot-through. This start-up procedure can be initiated by the supply voltage and/or the chip enable command by the circuit in Figure 37. FIGURE 36. FIGURE 37. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 BHB BHI DIS VSS BLI ALI HDEL AHI LDEL AHB BHO BLO BLS VDD BHS VCC ALS ALO AHS AHO 3.3K R2 ENABLE R1 15K 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 BHB BHI DIS VSS BLI ALI HDEL AHI LDEL AHB BHO BLO BLS VDD BHS VCC ALS ALO AHS AHO 3.3K R2 R1 15K ENABLE 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 BHB HEN DIS VSS OUT IN+ HDEL IN- LDEL AHB BHO BLO BLS VDD BHS VCC ALS ALO AHS AHO 100K RDEL RDEL VDD 0.1 F 2N3906 VDD ENABLE VDD 56K 8.2V 56K 100K |
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