DATASHEET

3.3V/2.5V 1:11 LVCMOS Zero Delay

Clock Generator

MPC9352

MPC9352 REVISION 8 MARCH 14, 2016

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©2016 Integrated Device Technology, Inc.

The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator

targeted for high performance clock tree applications. With output frequencies up

to 200 MHz and output skews lower than 200 ps, the device meets the needs of

most demanding clock applications.

Features

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Configurable 11 Outputs LVCMOS PLL Clock Generator

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Fully Integrated PLL

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Wide Range of Output Clock Frequency of 16.67 MHz to 200 MHz

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Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3

 2, 2  3,

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 3 and 1  2

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2.5 V and 3.3 V LVCMOS Compatible

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Maximum Output Skew of 200 ps

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Supports Zero-Delay Applications

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Designed for High-Performance Telecom, Networking and Computing

Applications

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32-Lead LQFP Package, Pb-Free

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Ambient Temperature Range –40°C to +85°C

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For functional replacement use 8T49N285

The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and clock driver. The device has the capability to gen-

erate output clock signals of 16.67 to 200 MHz from external clock sources. The internal PLL is optimized for its frequency range

and does not require external lock filter components. One output of the MPC9352 has to be connected to the PLL feedback input

FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-

cation factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its

specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx

pins supporting systems with different, but phase-aligned, clock frequencies.

The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and out-

puts are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50

 transmission lines. Alternatively, each

output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.

The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The

MPC9352 is packaged in a 32 ld LQFP.

MPC9352

LOW VOLTAGE

3.3 V/2.5 V LVCMOS 1:11

CLOCK GENERATOR

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016