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MPC9449 Datasheet(PDF) 1 Page - Renesas Technology Corp

Part # MPC9449
Description  3.3 V/2.5 V 1:15 PECL/LVCMOS Clock Fanout Buffer
PDF  12 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

MPC9449 Datasheet(HTML) 1 Page - Renesas Technology Corp

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DATASHEET
3.3 V/2.5 V 1:15 PECL/LVCMOS Clock
Fanout Buffer
MPC9449
MPC9449 REVISION 6 MARCH 15, 2016
1
©2016 Integrated Device Technology, Inc.
The MPC9449 is a 3.3 V or 2.5 V compatible, 1:15 clock fanout buffer targeted
for high performance clock tree applications. With output frequencies up to
200 MHz and output skews less than 200 ps the device meets the needs of the
most demanding clock applications.
Features
•
15 LVCMOS compatible clock outputs
•
Two selectable LVCMOS and one differential LVPECL compatible clock
inputs
•
Selectable output frequency divider (divide-by-one and divide-by-two)
•
Maximum clock frequency of 200 MHz
•
Maximum clock skew of 200 ps
•
High-impedance output control
•
3.3 V or 2.5 V power supply
•
Drives up to 30 series terminated clock lines
•
Ambient temperature range –40
C to +85C
•
52-lead LQFP packaging, Pb-free
•
Supports clock distribution in networking, telecommunication and computing
applications
•
Pin and function compatible to MPC949
•
For functional replacement use 8T49N285A
Functional Description
The MPC9449 is specifically designed to distribute LVCMOS compatible clock
signals up to a frequency of 200 MHz. The device has 15 identical outputs,
organized in four output banks. Each output bank provides a retimed or
frequency divided copy of the input signal with a near zero skew. The output
buffer supports driving of 50
 terminated transmission lines on the incident edge: each output is capable of driving either one
parallel terminated or two series terminated transmission lines.
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the
OE control will force the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports
a 2.5 V or 3.3 V power supply and an ambient temperature range of –40
C to +85C. The MPC9449 is pin and function
compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
3.5 V/2.5 V 1:15
PECL/LVCMOS
CLOCK FANOUT BUFFER
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016


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