S12SCIV3SLASHD datasheet(52/98 Pages) NXP

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MC9S12KG128 SoC Guide — V01.01

Section 14 Port Integration Module (PIM) Block Description

Consult the PIM_9KG128 Block Guide for information about the Port Integration Module.

Section 15 Pulse Width Modulator (PWM) Block Description

Consult the PWM_8B8C Block Guide for information about the Pulse Width Modulator Module. When

the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.

Section 16 Serial Communications Interface (SCI) Block

Description

There are two Serial Communications Interface modules (SCI1 and SCI0). Consult the SCI Block Guide

for information about the Serial Communications Interface module.

Section 17 Serial Peripheral Interface (SPI) Block

Description

There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12KG128.

Consult the SPI Block User Guide for information about each Serial Peripheral Interface module.

Section 18 Timer (TIM) Block Description

Consult the TIM_16B8C Block Guide for information about the Timer module. When the TIM_16B8C

Block Guide refers to freeze mode this is equivalent to active BDM mode.

Section 19 Voltage Regulator (VREG) Block Description

Consult the VREG_3V3 Block Guide for information about the dual output linear voltage regulator.

19.1 Device-specific information

19.1.1 VDD1, VDD2, VSS1, VSS2

In both the 112 pin LQFP and the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V

domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1

Freescale Semiconductor, Inc.

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S12SCIV3/D Datasheet(PDF) 52 Page - NXP Semiconductors