MPC962305 datasheet(2/19 Pages) RENESAS

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MPC962305 REVISION 8 3/15/16

MPC962305 Data Sheet

LOW-COST, 3.3V ZERO DELAY BUFFEr

Table 1. Pin Description for MPC962309

Signal

Description

1REF(1)

1. Weak pull-down.

Input reference frequency, 5 V-tolerant input

CLKA1(2)

2. Weak pull-down on all outputs.

Buffered clock output, Bank A

CLKA2(2)

Buffered clock output, Bank A

4VDD

3.3 V supply

GND

Ground

CLKB1(2)

Buffered clock output, Bank B

CLKB2(2)

Buffered clock output, Bank B

8S2(3)

3. Weak pull-ups on these inputs.

Select input, bit 2

9S1(3)

Select input, bit 1

CLKB3(2)

Buffered clock output, Bank B

CLKB4(2)

Buffered clock output, Bank B

GND

Ground

VDD

3.3 V supply

CLKA3(2)

Buffered clock output, Bank A

CLKA4(2)

Buffered clock output, Bank A

CLKOUT(2)

Buffered output, internal feedback on this pin

Table 2. Pin Description for MPC962305

Signal

Description

REF(1)

1. Weak pull-down.

Input reference frequency, 5 V-tolerant input

CLK2(2)

2. Weak pull-down on all outputs.

Buffered clock output

CLK1(2)

Buffered clock output

GND

Ground

CLK3(2)

Buffered clock output

VDD

3.3 V supply

CLK4(2)

Buffered clock output

CLKOUT(2)

Buffered clock output, internal feedback on this pin

CLKOUT

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

REF

CLKA1

CLKA2

VDD

GND

CLKB1

CLKB2

SOIC/TSSOP

Top View

Pin Configuration

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

CLKOUT

PLL

MUX

Select Input

Decoding

REF

Block Diagram

CLKOUT

CLK4

VDD

CLK3

REF

CLK2

CLK1

GND

SOIC/TSSOP

Top View

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