ADF4002 datasheet(17/24 Pages) AD

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ADF4002

Rev. 0 | Page 17 of 24

APPLICATIONS

VERY LOW JITTER ENCODE CLOCK FOR HIGH

SPEED CONVERTERS

Figure 21 shows the ADF4002 with a VCXO to provide the

encode clock for a high speed analog-to-digital converter (ADC).

The converter used in this application is an AD9215-80, a 12-bit

converter that accepts up to an 80 MHz encode clock. To realize

a stable low jitter clock, use a 77.76 MHz, narrow band VCXO.

This example assumes a 19.44 MHz reference clock.

To minimize the phase noise contribution of the ADF4002, the

smallest multiplication factor of 4 is used. Thus, the R divider is

programmed to 1, and the N divider is programmed to 4.

The charge pump output of the ADF4002 (Pin 2) drives the

loop filter. The loop filter bandwidth is optimized for the best

possible rms jitter, a key factor in the signal-to-noise ratio

(SNR) of the ADC. Too narrow a bandwidth allows the VCXO

noise to dominate at small offsets from the carrier frequency.

Too wide a bandwidth allows the ADF4002 noise to dominate at

offsets where the VCXO noise is lower than the ADF4002 noise.

Thus, the intersection of the VCXO noise and the ADF4002 in-

band noise is chosen as the optimum loop filter bandwidth.

The design of the loop filter uses the ADIsimPLL (Version 3.0)

and is available as a free download from www.analog.com/pll.

The rms jitter is measured at <1.2 ps. This level is lower than

the maximum allowable 6 ps rms required to ensure the

theoretical SNR performance of 59 dB for this converter.

The setup shown in Figure 21 using the ADF4002, AD9215, and

HSC-ADC-EVALA-SC, allows the user to quickly and

effectively determine the suitability of the converter and encode

clock. The SPI® interface is used to control the ADF4002, and

the USB interface helps control the operation of the AD9215-

80. The controller board sends back FFT information to the PC

that, if using an ADC analyzer, provides all conversion results

from the ADC.

VCXO: 77.76MHz

HC-ADC-EVALA-SC

TCXO:

19.44MHz

ENCODE

CLOCK

AIN

ADF4002

N = 4

R = 1

SPI

AGILENT:

500kHz, 1.8V p-p

AD9215-80

Figure 21. ADF4002 as Encode Clock

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