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HC908LD64AD/D Datasheet(PDF) 2 Page - NXP Semiconductors

Part # HC908LD64AD/D
Description  MC68HC908LD64 Technical Data
PDF  2 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC908LD64AD/D Datasheet(HTML) 2 Page - NXP Semiconductors

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HC908LD64AD/D
Page 279:
Correct OSDD[15:0] description under 18.7.3 OSD Data Registers.
From:
OSDD[15:0] — OSD RAM 16-Bit Data Buffer
These bits store the data which is going to be written into the OSD
RAM when OSDMEN is set. While OSD circuitry is displaying data
from the display RAM, updates to the display RAM is made by writing
to the OSD row and column address registers and this 8-bit pair data
registers. The OSD buffer write ready bit, WRDY, will be cleared after
the write to the high byte register, $0063.
To:
OSDD[15:0] — OSD RAM 16-Bit Data Buffer
While OSD circuitry is displaying data from the display RAM, update
the display RAM (location specified by the row and column address
registers, OSDRAR and OSDCAR) by writing data to the high byte
register (OSDDRH) followed by the low byte register (OSDDRL). After
writing to the OSDDRL, the OSD buffer write ready bit (WRDY) will be
cleared. WRDY becomes set again when the OSD circuitry has
transferred the content of the OSD data registers to the display RAM.
Page 288:
Correct OSD_EN bit location under 18.8.3.5 Frame Control Registers
From:
Row 15, Column 15:
To:
Row 15, Column 15:
76543210
HPOL
VPOL
15
14
13
12
11
10
9
8
OSD_EN
76543210
HPOL
VPOL
15
14
13
12
11
10
9
8
OSD_EN
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