AD7652 datasheet(23/32 Pages) AD

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AD7612

Rev. 0 | Page 23 of 32

Power Sequencing

The AD7612 is independent of power supply sequencing and is

very insensitive to power supply variations on AVDD over a wide

frequency range as shown in Figure 31.

10000

FREQUENCY (kHz)

100

1000

EXT REF

INT REF

Figure 31. AVDD PSRR vs. Frequency

Power Dissipation vs. Throughput

In impulse mode, the AD7612 automatically reduces its power

consumption at the end of each conversion phase. During the

acquisition phase, the operating currents are very low, which allows

a significant power savings when the conversion rate is reduced

(see Figure 32). This feature makes the AD7612 ideal for very

low power, battery-operated applications.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital supply

currents even further, drive the digital inputs close to the power

rails (that is, OVDD and OGND).

1000

SAMPLING RATE (kSPS)

100

WARP MODE POWER

IMPULSE MODE POWER

PDREF = PDBUF = HIGH

Figure 32. Power Dissipation vs. Sample Rate

Power Down

Setting PD = high powers down the AD7612, thus reducing

supply currents to their minimums as shown in Figure 23. When

the ADC is in power down, the current conversion (if any) is

completed and the digital bus remains active. To further reduce

the digital supply currents, drive the inputs to OVDD or OGND.

Power down can also be programmed with the configuration

that when using the configuration register, the PD input is a

don’t care and should be tied to either high or low.

CONVERSION CONTROL

The AD7612 is controlled by the CNVST input. A falling edge

on CNVST is all that is necessary to initiate a conversion. Detailed

timing diagrams of the conversion process are shown in Figure 33.

Once initiated, it cannot be restarted or aborted, even by the

power-down input, PD, until the conversion is complete. The

CNVST signal operates independently of CS and RD signals.

BUSY

MODE

CONVERT

ACQUIRE

CONVERT

CNVST

Figure 33. Basic Conversion Timing

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot, undershoot, or ringing.

The CNVST trace should be shielded with ground and a low value

(such as 50 Ω) serial resistor termination should be added close

to the output of the component that drives this line.

For applications where SNR is critical, the CNVST signal should

have very low jitter. This can be achieved by using a dedicated

oscillator for CNVST generation, or by clocking CNVST with a

high frequency, low jitter clock, as shown in Figure 27.

AD7652 Datasheet(PDF) 23 Page - Analog Devices

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