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AN2701 Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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AN2701 Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 14 page ![]() PWM Period (timer ticks) Bus Frequency Timer Prescaler PWM Frequency × --------------------------------------------------------------------------------------------- = PWM Mark Time (timer ticks) PWM Period Duty Cycle (as an integer percentage) × 100 --------------------------------------------------------------------------------------------------------------------------------------------- = PWM Space Time (timer ticks) PWM Period PWM Mark Time – = PWM Generation During Break or Software Interrupt PWM Generation with the HC08 Timer, Rev. 0 Freescale Semiconductor 9 Eq. 1 Eq. 2 Eq. 3 Once the timer channel is configured, the PWM signal can be generated using the timer channel interrupt. This should be configured to call the channel interrupt service routine (ISR), loading the timer compare register with its current value added to the length desired (mark or space). This is achieved by identifying whether the last action was a negative or positive edge (the port pin toggles on output compare), and loading the compare register with the next appropriate value. If the port pin is at logic one (or zero), a mark (or space) is to be added. NOTE In this case, the overflow flag and interrupt are not relevant as the counter is used as free-running with roll-over. The sample code in the appendix at the end of this document gives an example of how to apply this principle. Limitations The MCU must be able to service the timer PWM interrupts in time for the next edge to be configured. This sets an upper limit on the frequency/resolution of PWM signal that can be reproduced, and will vary from system to system depending on the MCU application. It is the responsibility of the system designer to ensure that the core can update the compare registers in sufficient time using the ISR under maximum core loading conditions. A secondary limitation is that using the timer module incurs a greater degree of core overhead, as the timer module has to be serviced at every edge transition (interrupt). This does not happen with the unbuffered PWM via modulo counter, as the toggling mechanism is independent of the core and code execution. The described method of PWM generation is likely to be more suited to slower rate PWM requirements, due to the overhead generated by having to service an interrupt for each edge of each PWM signal. PWM Generation During Break or Software Interrupt The HC08 data sheet states that the timer is stopped during a break. It is important to distinguish a Break from a software interrupt (SWI) instruction. The Break Module (BRK) is primarily used in a debugging/development context. For example, breakpoints in monitor mode are generated using this module. This explains why the debugger stops program execution when an address match or BRKA bit-mask is performed. |
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