LP2985IM5-3.3 datasheet(27/43 Pages) TI

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Figure 8-25. Turn-On Time for Legacy Chip

2 ms/div

-4

-3

-2

-1

V0= 3.3 V

Cbyp = 1nF

ILOAD = 150mA

VON

COUT = 4.7 μF

Figure 8-26. Turn-On Time for New Chip

Figure 8-27. Turn-On Time for Legacy Chip

20ms/div

100

120

-4

-3

-2

-1

V0 = 3.3 V

Cbyp = 10 nF

ILOAD = 150 mA

VOUT

VON

COUT = 4.7 μF

Figure 8-28. Turn-On Time for New Chip

8.3 Power Supply Recommendations

A power supply can be used at the input voltage within the ranges given in the Recommended Operating

Conditions table. Use bypass capacitors as described in the Layout Guidelines section.

8.4 Layout

8.4.1 Layout Guidelines

For best overall performance, place all circuit components on the same side of the circuit board and as near

as practical to the respective LDO pin connections. Place ground return connections to the input and output

capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,

copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and

negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and

thereby reduces load-current transients, minimizes noise, and increases circuit stability.

A ground reference plane is also recommended and is either embedded in the PCB or located on the bottom

side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage,

shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most

applications, this ground plane is necessary to meet thermal requirements.

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LP2985-N

SNVS018Z – MARCH 2000 – REVISED MAY 2023

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