ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2

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Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

United States

800 345 7015

+408 284 8200 (outside U.S.)

© 2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks

of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks

are or may be trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA

Revision History

Rev.

Originator Issue Date Description

Page #

F

8/6/2007

1. Added Phase Noise Parameters, Updated input to output delay values.

2. PLL BW moved to PLL parameters table.

3. Added terminations tables.

Various

G

12/14/2007 Updated General SMBus Interface Information.

8

H

10/29/2008 Corrected "HCSL" typos.

1, 6, 7

J

1/15/2010

1. Added I-temp electricals

2. Changed datasheet title

3. Updated Input Frequency parameter

4. Updated ordering information

Various

K

RW

4/1/2010

Updated ordering info for Rev B

L

DC

9/28/2010 Updated package dimension tables

11, 12

M

RDW

1/27/2011 Updated Termination Figure 4.

7

N

RDW

4/20/2011

Changed pulldown indicator on CLKREQ# pins to correct pin description of

those pins.

P

AT

5/24/2012 Added OE# Latency spec to Common Input/Output Parameters table

3

Q

J. Chao

8/27/2013 Updated PLL Bandwidth specs per latest characterization data,

3