IDT5V19EE604

EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

CLOCK SYNTHESIZER

IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

14

IDT5V19EE604

REV M 092412

Progread

Note: If the expected read command is not from the next higher register to the previous read or write command, then set a

known “read” register address prior to a read operation by issuing the following command:

Prior to Progread Command Set Register Address

The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave

acknowledgement bit (i.e., followed by the Progread command):

Progread Command Frame

Progsave

Note:

PROGWRITE is for writing to the IDT5V19EE604 registers.

PROGREAD is for reading the IDT5V19EE604 registers.

PROGSAVE is for saving all the contents of the IDT5V19EE604 registers to the EEPROM.

PROGRESTORE is for loading the entire EEPROM contents to the IDT5V19EE604 registers.

Progrestore

EEPROM Interface

The IDT5V19EE604 can also store its configuration in an internal EEPROM. The contents of the device's internal

programming registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to

the internal programming registers by issuing a restore instruction (ProgRestore).

To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit

set to “0”, followed by the appropriate command code. The save or restore instruction executes after the STOP condition is

issued by the Master, during which time the IDT5V19EE604 will not generate Acknowledge bits. The IDT5V19EE604 will

acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted

as busy by all other users of the bus.

On power-up of the IDT5V19EE604, an automatic restore is performed to load the EEPROM contents into the internal

programming registers. The IDT5V19EE604 will be ready to accept a programming instruction once it acknowledges its 7-bit

I2C address.

SAddress

R/W

ACK

Command Code

ACK

Register

ACK

P

7-bits

0

1-bit

8-bits: xxxx xx00

1-bit

8-bits

1-bit

SAddress

R/W

ACK

ID Byte

ACK

Data_1

ACK

Data_2

ACK

Data_last

NACK

P

7-bits

1

1-bit

8-bits

1-bit

8-bits

1-bit

8-bits

1-bit

8-bits

1-bit

SAddress

R/W

ACK

Command Code

ACK

P

7-bits

0

1-bit

8-bits: xxxx xx01

1-bit

SAddress

R/W

ACK

Command Code

ACK

P

7-bits

0

1-bit

8-bits: xxxx xx10

1-bit