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70P246A55BYAI Datasheet(PDF) 1 Page - Renesas Technology Corp |
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70P246A55BYAI Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 24 page ![]() 1 ©2009 Integrated Device Technology, Inc. JANUARY 2009 DSC-5699/2 I/O Control Address Decoder A12L(1) A0L MEMORY ARRAY ARBITRATION INTERRUPT SEMAPHORE LOGIC OEL R/ WL CEL 5699 drw 01 OER R/ WR CER SEML INTL SEMR INTR 13 13 A12R(1) A0R Address Decoder I/O Control BUSYL I/O8L-I/O15L I/O0L-I/O7L BUSYR I/O8R-I/O15R I/O0R-I/O7R (2) (2) , INPUT READ REGISTER AND OUTPUT DRIVE REGISTER OEL R/ WL CEL OER R/ WR CER IRR0,IRR1 OD R0 - ODR4 R/ WL UBL LBL CEL OEL R/ WR UBR LBR CER OER SFEN (2) (2) PRELIMINARY IDT70P256/246L VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Industrial: 55ns (max.) ◆ ◆ ◆ ◆ ◆ Low-power operation IDT70P256/246L Active: 27mW (typ.) Standby: 3.6 µW (typ.) ◆ ◆ ◆ ◆ ◆ Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ Supports 3.0V and 2.5V I/O's ◆ ◆ ◆ ◆ ◆ Input Read Register ◆ ◆ ◆ ◆ ◆ Output Drive Register ◆ ◆ ◆ ◆ ◆ BUSY and Interrupt Flag ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, single 1.8V (±100mV) power supply ◆ ◆ ◆ ◆ ◆ Available in 100 Ball 0.5mm-pitch BGA ◆ ◆ ◆ ◆ ◆ Industrial temperature range (-40°C to +85°C) ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information Functional Block Diagram NOTES: 1. A12X is a NC for IDT70P246. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. |
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