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AT90SC6436RT

6505AS–SMIC–30Mar04

Description

tecture, with flexible ROM program memory and EEPROM data memory. By executing powerful instructions in a single

clock cycle, the AT90SC6436RT achieves throughputs close to 1 MIPS per Mhz. Its Harvard architecture includes 32 gen-

eral-purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one

single instruction executed in one clock cycle.

The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system.

This technology combined with the versatile 8/16-bit CPU on a monolithic chip provides a highly flexible and cost-effective

solution to many smartcard applications.

The AT90SC6436RT can also be configured to offer compatibility with the AT90SC6432R.

Figure 1 shows the AT90SC6436RT block diagram.

Figure 1. AT90SC6436RT secureAVR Enhanced RISC Architecture

Secure

Control

VCC

GND

CLK

Access

Control

Data Bus

8-bit

RNG

IN/OUT0

Reset

Circuit

RST

Timer

RAM

Data Memory

Interrupt

Unit

ISO 7816

I/O Port 0

On-Chip

Security

Access

Control

General

Purpose

Registers

X

Y

Z

Status

Register

ALU

Instruction

Decoder

Flash Program

Memory

Instruction

Register

Control

Lines

EEPROM

User Memory

OTP

PC

16

16

16

8

88