5

ICS95V842

0830B—11/24/08

Notes:

1.

2.

3.

4. Does not include jitter.

Switching characteristics are guaranteed for application frequency range. The

PLL Locks over the Max Clock Frequency range, but the device doe not

necessarily meet other timing parameters.

Refers to transition on noninverting output in PLL bypass mode.

While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,

were the cycle (tc) decreases as the frequency goes up.

Switching Characteristics

TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Max clock frequency

3

freqop

40

333

MHz

Application Frequency

Range

3

freqApp

60

220

MHz

Input clock duty cycle

dtin

40

60

%

Input clock slew rate

tsl(I)

12

v/ns

CLK stabilization

TSTAB

100

µs

Low-to high level propagation

delay time

tPLH

1

CLK_IN to any output

5.5

ns

High-to low level propagation

delay time

tPHL

1

CLK_IN to any output

5.5

ns

Output enable time

ten

PD# to any output

5

ns

Output disable time

tdis

PD# to any output

5

ns

Period jitter

tjit (per)

-75

75

ps

Half-period jitter

tjit(hper)

-75

75

ps

Output clock slew rate

tsl(o)

12.5

v/ns

Cycle to Cycle Jitter

tcyc-tcyc

-75

75

ps

Static Phase Offset

t(spo)

-50

50

ps

Output to Output Skew

tskew

40

60

ps

Over the application

frequency range