DATASHEET

LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

ICS601-25

IDT™ / ICS™ LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

1

ICS601-25

REV E 051310

Description

The ICS601-25 is a low-cost, low phase noise, high

performance clock synthesizer for applications which

require low phase noise, low jitter, and low skew fanout. It is

IDT’s lowest phase noise multiplier, and also the lowest

CMOS part in the industry. Using IDT’s patented analong

and digital Phase Locked Loop (PLL) techniques, the chip

accepts a 10-27 MHz crystal or clock input, and produces

output clocks up to 156 MHz.

Features

• Packaged in 20-pin SSOP

• Uses fundamental 10 - 27 MHz crystal or clock

• Output clocks up to 156 MHz

• Low phase noise: -132 dBc/Hz at 10 kHz

• Five low skew (<250 ps) outputs

• Low jitter - 18 ps one sigma at 125 MHz

• Full swing CMOS outputs with 25 mA drive capability at

TTL levels

• Powerdown mode lowers power consumption

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• Pb (lead) free package

• Operating voltage of 3.3 V

Block Diagram

CLK1

ROM Based

Multipliers

VCO

Divide

X1/ICLK

X2

Crystal or

clock input

Crystal

Oscillator

Reference

Divider

Phase

Comparator

VDD

Charge

Pump

Loop

Filter

VCO

S3:0

PD

CLK5

CLK4

CLK3

CLK2

5

GND

3

4