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ICS650-12 Datasheet(PDF) 2 Page - Renesas Technology Corp |
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ICS650-12 Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 8 page ![]() ICS650-12 MPEG CLOCK SYNTHESIZER CLOCK SYNTHESIZER IDT™ / ICS™ MPEG CLOCK SYNTHESIZER 2 ICS650-12 REV E 051310 Pin Assignment PCLK1 and PCLK2 Select Table (in MHz) ACLK Select Table (in MHz) CCLK Select Table (in MHz) *Note: Entire chip powers-down (outputs stop low) when CS1=CS0=0. PS2 PS1 PS0 PCLK1 PCLK2 0 0 0 108.00 54.00 0 0 1 55.00 27.5 0 1 0 66.67 33.33 0 1 1 80.00 40.00 1 0 0 54.00 27.00 1 0 1 81.00 40.5 1 1 0 50.00 25.00 1 1 1 60.00 30.00 13 4 12 5 11 CS1 8 9 10 VDD PCLK1 13.5M AS0 CS0 27M 17 16 AS2 3 X1 VDD PCLK2 18 CCLK 1 PS2 X2 PS0 20 PS1 19 14 2 7 GND ACLK AS1 GND 15 6 20-pin SSOP (QSOP) AS2 AS1 AS0 ACLK 0 0 0 12.288 0 0 1 11.2896 0 1 0 8.192 0 1 1 24.576 1 0 0 8.192 1 0 1 16.9344 1 1 0 18.432 1 1 1 11.2896 CS1 CS0 CCLK 00All off* 01 20.00 1 0 66.6666 1 1 24.576 |
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