ICS650-14

NETWORKING SYSTEM CLOCK

CLOCK SYNTHESIZER

IDT™ / ICS™ NETWORKING SYSTEM CLOCK

2

ICS650-14

REV H 051310

Pin Assignment

Table 2

Table 1

Table 3

0 = connect directly to ground

1 = connect directly to VDD

M = leave unconnected (floating)

Pin Descriptions

SELB1

SELB0

CLKB

00

30

0M

27

01

48

10

83.33

1M

19.44

11

80

13

4

12

5

11

SELB1

8

9

10

VDD

CLKC

CLKA4

OE

CLKA5

CLKA1

17

16

25M

3

X1/ICLK

VDD

CLKA3

18

CLKA2

1

SELB0

X2

SELA0

20

SELC

19

14

2

7

GND

CLKB

SELA1

GND

15

6

20-pin (150 mil) SSOP

SELA1

SELA0

CLKA1:4

CLKA5

0

0

33.33

66.66

0M

50

75

0

1

66.67

133.33

M

0

100

33.33

M

M

33.33

83.33

M

1

50

125

10

33.33

100

1M

25

75

11

66.67

100

SELC

CLKC

0

CLKB/4

M

62.5

1125

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

SELB0

TI

Select pin for CLKB. See table 2.

2

X2

XO

Crystal connection. Connect to a 25 MHz crystal or leave unconnected for clock

input.

3

X1/ICLK

XI

Crystal connection. Connect to a 25 MHz fundamental crystal or clock input.

4

VDD

P

Connect to 3.3 V or 5 V. Must be same as other VDDs.

5

SELB1

I(Pu)

Select pin for CLK B. See table 2.

6

GND

P

Connect to ground.

7

CLKB

O

Selectable clock output. See table 2.

8

CLKC

O

Selectable clock output. See table 3.

9

CLKA5

O

Selectable clock output. See table 1.

10

25M

Ou

25 MHz clock output.

11

OE

I(Pu)

Output enable. Tri-states all outputs when low. Internal pull-up.

12

CLKA1

O

Selectable clock output. See table 1.